1. Field of the Invention
This invention relates broadly to clock skew. More particularly, this invention relates to testing the accuracy of Delay Locked Loops (DLLs) used in Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM) interfaces.
2. State of the Art
DDR SDRAM is used in a wide variety of applications including high speed telecommunications. This type of SDRAM achieves double the bandwidth of conventional SDRAM by transferring data on both the rising and failing edges of a clock signal. A typical DDR SDRAM transfers eight bytes at each transfer. Thus, a DDR SDRAM running at 100 MHz has a transfer bandwidth of approximately 1.6 GB per second. In order to function correctly, the data and clock edges must be precisely aligned. This alignment is achieved with a DLL together with a PLL (Phase Locked Loop) in the DDR memory interface.
A DLL is similar to a PLL (Phase Locked Loop) but without an oscillator. It can be used to change the phase of a clock signal. A DLL includes a chain of delay gates. The number of gates determines how much the phase of the input clock signal is changed. For a DDR SDRAM, the DLL performs a 90° and 270° phase shift. The first memory access is performed on the 90° clock edge and the second is performed on the 270° clock edge. If the phase difference is not accurate, data transfer to/from the SDRAM will fail.
Memory interfaces including DLLs are often part of a larger more complex circuit on a single CMOS semiconductor chip. The amount of delay in a CMOS cell is affected by the fabrication process, operating voltage and temperature and a fault in a DLL can render the entire chip useless. Unfortunately, DLL circuits are very difficult to test because the signals between the delay elements are essentially the same, just delayed. Thus, conventional structural testing via scan chains cannot distinguish between certain failures, like a short between outputs of delay elements that would not result in 180/360 degree phases. This is also true for clock trees which are meant to generate multiple clocks of the same phase all over a chip. Current testing solutions rely on a sliding window sampling technique to extract jitter characteristics. While these techniques are accurate, they are elaborate. A simpler test would be desirable.